Galibert, does this seem to line up with the addressing behavior you noted?
FM_write does a bit of software delay for 6 NOP's (12 cycles; 4.8us) before beginning a polling operation to wait for the hardware to become ready for the transaction. Once the 'busy' bit clears the data is sent to 0x200.
This feels like it's a slow bus device that is polled with software. At first I was thinking it would have been smarter for it to use the 65c02 core's RDY input to stall the CPU, but there's other code that polls the busy bit and returns if it's set for events that have to be closer to real-time.
Also, some more code references have been fixed. For The Moment(TM) there aren't any invalid jumps, which will help identify base addresses of data tables in the ram, as well as IO device usage by routines in the firmware.
Looks like this coming week will be spent researching the YM series FM chips to search for commonalities with this type of behavior. Thankfully there's tons of examples in the wild, some even on the Commodore 64 in case I need a similar CPU.

-jbev