I'm working with the VGM format and I'm very confused by the SN76489 series LFSR bit count, which is apparently based directly on MAME's implementation. As I understand it, real SN76489-series chips are 15-bit LFSR and some custom versions are 16-bit. But in MAME some discrete chips have a feedback mask of 0x10000 (implying 17-bit) despite the comments in the same file making no mention of a variant having 17-bit LFSR. What is going on here?
EDIT: Some additional information: The SMSPower article only shows noise patterns for 15-bit and 16-bit. Based on the list of patterns people donated for the article, it should include several systems that use the SN76489AN, which is thought to be the same as SN76489A, but SN76489A is supposed to be 17-bit.
Re: SN76489 Series LFSR Confusion
Okay, I talked to Lord_Nightmare and got the answers I needed. The feedback mask is not the same thing as the number of LFSR bits, it's the LFSR bits + latency bits. So-called "17-bit" chips are 15-bit chips that have 2 bits of latency, as can be seen by the tap masks of 4 and 8 rather than 1 and 2.
Currently talking to ValleyBell to determine whether VGMs that specify 17-bit LFSR (the entire reason I got started looking into this) should be regarded as invalid and added to the queue to be fixed.
Currently talking to ValleyBell to determine whether VGMs that specify 17-bit LFSR (the entire reason I got started looking into this) should be regarded as invalid and added to the queue to be fixed.
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Lord Nightmare
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- Joined: Thu Nov 06, 2014 1:21 pm
Re: SN76489 Series LFSR Confusion
We discussed this on IRC last night. In short (and this matches what was posted above):
Some of the LFSR variants in sn764xx and other PSG chips have clocked latches after the LFSR causing a 1-3 bit delay before the most recent lfsr bit is actually used. The LFSR is implemented as a rightward-shifting fibonacci LFSR with the optionally-per-device-inverted output tap on bit 0. On some devices like SN76489A, the feedback bit may be the bit masked by 0x10000, which implies that the LFSR is actually 17 bits long, but the XOR tap bits are on bits 0x04 and 0x08, so it effectively acts as a 15 bit long LFSR with two extra delayed bits (in bits 0(mask 0x01) and 1(mask 0x02)), which matches the device behavior.
Some of the LFSR variants in sn764xx and other PSG chips have clocked latches after the LFSR causing a 1-3 bit delay before the most recent lfsr bit is actually used. The LFSR is implemented as a rightward-shifting fibonacci LFSR with the optionally-per-device-inverted output tap on bit 0. On some devices like SN76489A, the feedback bit may be the bit masked by 0x10000, which implies that the LFSR is actually 17 bits long, but the XOR tap bits are on bits 0x04 and 0x08, so it effectively acts as a 15 bit long LFSR with two extra delayed bits (in bits 0(mask 0x01) and 1(mask 0x02)), which matches the device behavior.
Re: SN76489 Series LFSR Confusion
Just in case anybody wants to know how the story ends, ValleyBell decided that to retain compatibility with existing packs made with the misunderstanding about MAME's mask values, VGM's LFSR width == MAME's feedback mask and VGM's feedback mask == MAME's tap points. The spec has been updated accordingly.